Dataset for "Displacement Talbot Lithography for nano-engineering of III-nitride materials"

Dataset for "Displacement Talbot Lithography for nano-engineering of III-nitride materials"

This dataset contains scanning electron microscopy (SEM) images of various nano-patterns. The nano-patterns are first created in the resist via Displacement Talbot Lithography. The nano-patterns in the resist are then used to create dielectric or metal mask, respectively via Inductively coupled plasma dry etching or lift-off. Finally, the masks are employed either for the bottom-up selective area growth (via metal organic vapour phase epitaxy) or for the top-down fabrication of nanostructures. A combination of top-down etching and bottom-up can also be employed.

Subjects:
Electrical engineering
Materials sciences

Cite this dataset as:
Coulon, P., 2019. Dataset for "Displacement Talbot Lithography for nano-engineering of III-nitride materials". Bath: University of Bath Research Data Archive. Available from: https://doi.org/10.15125/BATH-00696.

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Data

Fig1.pdf
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Inset in Fig6.a has been extracted from the linked YouTube video of selective area sublimation within a MBE chamber.

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Creators

Pierre-Marie Coulon
University of Bath

Contributors

Philip Shields
Project Leader
University of Bath

University of Bath
Rights Holder

Documentation

Data collection method:

Secondary electron images were captured using a Hitachi S-4300 scanning electron microscope (SEM). An accelerating voltage of 5 kV was used to collect the images

Technical details and requirements:

All DTL patternings have been performed on 2-inch wafers (Figure 1.a). A stack of two layers was spin-coated at 3000 rpm to obtain a ~ 270 nm bottom antireflective coating (BARC) (Wide 30W – Brewer Science) layer thickness, followed by either a layer of high-contrast positive resist (Dow® Ultra-i 123 diluted with Dow® EC11 solvent) or a layer of negative resist (AZ® 15 NXT diluted with AZ® Edge Bead Remover (EBR) solvent with a 7:12 ratio by weight). The baking temperature is a critical parameter for the BARC processing as it determines the rate at which the BARC develops. A bake at 150°C enables a wet-developable process and thus to create an undercut profile (Fig. 1e and 3e). A bake at 200°C fully cures the BARC, making it insoluble in a developer (Fig. 1b). DTL (PhableR 100, Eulitha) was then used to expose the resist with a coherent 375 nm light source with an energy density of 1 mW.cm-2 (Fig. 1a). Various masks have been employed: two hexagonal amplitude masks, one with a 1.5 μm pitch with 800 nm diameter circular opening, and another with a 1 μm pitch with 550 nm opening, and two phase mask, one with a 500 nm pitch with 300 nm diameter circular opening, and another with lines spaced by 800 nm with a 62% filling factor. The Talbot length associated with those masks is 8.81 μm, 3.80 μm, 750 nm and 3.21 μm, respectively. Details of the calculation can be found in other publications. The gap between the mask and the wafer was set to 150 μm. A Gaussian velocity integration was applied and 8 Talbot lengths travel distance has been chosen to assure a homogenous integration on several Talbot motifs. After a certain exposure time (which defines the exposure dose), the sample was baked for 1 min 30 sec at 120°C on a hot plate. The wafer with a positive resist was developed in MF-CD-26 for 90 to 240 sec (depending on the mask fabrication), the one with a negative resist in AZ 726 for 30 sec. Finally, the wafer was rinsed with deionized water and dried with nitrogen. Materials such as hydrogen silsesquioxane (HSQ) and silicon nitride (SiNx) were used as a dielectric mask. Prior to DTL patterning, HSQ was spin-coated on 2-inch wafers at 3000 rpm and baked from 150°C to 450°C in 100°C increments or SiNx was deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD). The pattern created in the resist by DTL/D2TL (Fig. 1b and Fig. 2a-l) were transferred into the dielectric material (Fig. 1c and Fig. 3a-d) via an inductively coupled plasma (ICP) dry etch system (Oxford Instruments System 100 Cobra). The experiments were performed with a CHF3 chemistry of 25 sccm, a temperature set to 20 °C, a pressure of 8 mTorr, 50 RF power and 300 W ICP source power, resulting in a etch rate of ~50 nm/min. The etching time was adjusted as a function of the thickness of the dielectric mask. The resulting transferred pattern was then cleaned in a piranha solution (3:1) and oxygen plasma (Fig. 1d). The undercut profile created in the BARC (cured at 150°C) after exposure and development (Fig. 1e and Fig. 2e) was employed as a lift-off layer. 200 nm Ni layers were deposited via e-beam evaporation to produce metal masks in the circular opening at the surface of the wafer (Fig. 1f and Fig. 2f). Subsequent lift-off was achieved by soaking the wafer in MF-CD-26 developer. Finally, wafers were cleaned in a 2 min reactive-ion etching (RIE) oxygen plasma to remove any BARC residue (Fig. 1g and Fig. 2g-i). The selective area growth of InGaN/GaN core-shell nanorods has been carried out in a showerhead MOCVD reactor. The GaN core has been grown under continuous flow mode with the following conditions: A carrier gas mixture of N2 and H2 with H2/N2=2, a temperature of 1200°C, a total reactor pressure of 100 mbar, and the TMGa and NH3 flow rates fixed at 80 sccm. Other details about the growth conditions and optimization can be found in previous plublications. On the GaN nanorods, five periods of InGaN/GaN QWs have been deposited using standard QW growth conditions, TMIn, TEGa and NH3 have been used as precursors, pressure has been fixed at 400mbar and the growth temperature set between 850°C and 980°C for QWs and GaN Barriers, respectively. An ICP dry etch system was used to create nanostructures in various materials including GaN, AlN, III-Nitride LEDs structures and sapphire substrates. In the case of III-nitrides, the experiments were performed with a Cl2/Ar chemistry of 50/10 sccm, a temperature of 150°C, a pressure set between 9 to 15 mTorr, a RF power set between 80 and 120 W and 800 W ICP source power. More details can be found in previous publications. For sapphire substrate, the experiments were performed with a Cl2/BCl3/Ar chemistry of 5/50/5 sccm, a temperature of 5°C, a pressure of 8 mTorr, 100 W RF power and 600 W ICP source power. Finally, the masks were etched away in aqua-regia solution (HCl:HNO3, 3:1) for metal masks, and in BOE 5:1 for dielectric masks. The samples used for the selective area sublimation were grown on 2-inch c-plane (0001) sapphire substrates by MOCVD in a 7x2-inch close-coupled showerhead Aixtron reactor. A 2 µm non-intentionally doped GaN was first grown followed by a 2 µm Si- doped (5x1018 cm-3) GaN layer. The first 2 µm of GaN are undoped in order to favour the coalescence of the layer after an initial 3D growth mode to reduce the threading dislocation density. Displacement Talbot lithography is used to pattern a SiNx or a SiOx dielectric mask with respectively holes (Fig. 3b) or dots (Fig. 3d). The samples are annealed under vacuum in a MBE chamber during 3h at 910°C and 10h at 940°C for the samples with the hole pattern and the dot pattern, respectively. More details can be found in previous publications. The III-nitride bottom-up regrowth was carried out in a 1 x 2” horizontal Aixtron MOVPE reactor. The growth conditions for AlN faceting on nanorod were the following: a temperature of 1100°C, a pressure of 20 mbar, 10 sccm in TMAl flow rate, 4000 sccm in NH3 flow rate, and H2 as the carrier gas. GaN regrowth was performed at a temperature of 920°C (Fig. 7b) or 820 °C (Fig. 7c), a pressure of 100 mbar, 8 sccm in TMGa flow rate, 2800 sccm in NH3 flow rate, and H2 as the carrier gas. More details can be found in previous publications. AlN overgrowth on nanopillar-nPSS was done in an AIX2400G3HT MOVPE planetary reactor with a capability of 11 x 2-inch wafers with standard TMAl and NH3 precursors. Pressure was fixed at 50 mbar and H2 served as carrier gas. A 50 nm thick nucleation layer was deposited at 980 °C with a V/III ratio of 4000. After nucleation, the temperature was increased to 1380 °C with a V/III ratio of 30, followed by a decrease to 1180 °C with the same V/III ratio.

Funders

Engineering and Physical Sciences Research Council (EPSRC)
https://doi.org/10.13039/501100000266

Manufacturing nano-engineered III-nitrides
EP/M015181/1

Publication details

Publication date: 18 September 2019
by: University of Bath

Version: 1

DOI: https://doi.org/10.15125/BATH-00696

URL for this record: https://researchdata.bath.ac.uk/id/eprint/696

Related articles

Coulon, P.-M., Damilano, B., Alloing, B., Chausse, P., Walde, S., Enslin, J., Armstrong, R., Vézian, S., Hagedorn, S., Wernicke, T., Massies, J., Zúñiga‐Pérez, J., Weyers, M., Kneissl, M. and Shields, P. A., 2019. Displacement Talbot lithography for nano-engineering of III-nitride materials. Microsystems & Nanoengineering, 5(1). Available from: https://doi.org/10.1038/s41378-019-0101-2.

Contact information

Please contact the Research Data Service in the first instance for all matters concerning this item.

Contact person: Pierre-Marie Coulon

Departments:

Faculty of Engineering & Design
Electronic & Electrical Engineering

Research Centres & Institutes
Centre for Nanoscience and Nanotechnology